1. Field of the Invention
This invention generally relates to a power-saving method for Viterbi decoder and a bit processing circuit of a wireless receiver, and more specifically, to a power-saving method, wherein power is provided to the Viterbi decoder and the bit processing circuit based on various duty cycles of time pulse signals corresponding to various data rates applied by the wireless receiver.
2. Description of Related Art
In modern communication system, power consumption reduction has become an important issue that wireless receiver designers have to take into consideration. Especially to a mobile communication system, lower power consumption means that it takes longer time to consume up power of allocated battery, thereby providing user with more convenience.
Please refer to FIG. 1, which is a basic framework block diagram of a prior wireless receiver 10. The wireless receiver 10 is an orthogonal frequency division multiplexing (OFDM) receiver for wireless communication by means of orthogonal frequency division multiplexing technique. Briefly speaking, the orthogonal frequency division multiplexing technique divides a data string with high data rate into a plurality of data strings with low data rate, and then transmits the plurality of data strings with low data rate simultaneously via a plurality of subcarriers, thereby achieving high data rate transmission and resistance of frequency selective fading. The wireless receiver 10 comprises an antenna 12, a signal processing circuit 14, a Viterbi decoder 16, and a time pulse circuit 18. The antenna receives OFDM signal, and then the signal processing circuit 14 performs process of OFDM signal received by the antenna 12, e.g. filtering, time domain/frequent domain conversion, etc. In general, the Viterbi decoder is allocated to the modern communication system for performing Viterbi decoding process on signals transmitted from signal processing circuit 14, and the time pulse circuit 18 is used for producing enabling signal SE and time pulse signal Sa to control performances of the signal processing circuit 14 and the Viterbi decoder 16. The enabling signal SE enables the signal processing circuit 14 and the Viterbi decoder 16. In other words, only when the enabling signal SE is at high electric potential, the signal processing circuit 14 and the Viterbi decoder 16 are enabled to operate. In addition, time pulse signals Sa determine various operations of the signal processing circuit 14 and the Viterbi decoder 16.
In the prior art, power-saving strategy of wireless receiver 10 controls electric potential of the enabling signal SE. Please refer to FIG. 2, which is a time sequence diagram illustrating enabling signal SE and time pulse signal Sa produced by the time pulse circuit 18 of FIG. 1. During the time the wireless receiver 10 is receiving packets, e.g. time segments T1 and T2, the enabling signal SE is pulled up to a high electric potential, thereby enabling the signal processing circuit 14 and the Viterbi decoder 16 to operate and process the received packets. While at the time the wireless receiver 10 is in an idle state without receiving any packet, e.g. time segment T2, the enabling signal SE is pulled down to a low electric potential, thereby stopping the signal processing circuit 14 and the Viterbi decoder 16 from operating temporarily, so as to save power.
However, the aforementioned power-saving method of a wireless receiver is not ideal, and there are still some bases are overlooked, thereby causing unnecessary power consumption. For instance, data rate of wireless receiver varies with factors such as distance from sending device, etc., and when the data rate of wireless receiver changes, total data processed by the Viterbi decoder 16 during each processing cycle vary from one anther processing cycle accordingly. When the data rate of wireless receiver is high, the Viterbi decoder 16 might need time as long as the time segments T1 and T3 for performing a full decoding process. However, when the data rate of wireless receiver 10 is low, practical time needed for the Viterbi decoder 16 to perform the full decoding process is only partial the time segments T1 and T3 and is shorter than the time segments T1 and T3. Since the Viterbi decoder 16 is controlled by the time pulse signal Sa, when the Viterbi decoder 16 has completed the full decoding process, the Viterbi decoder 16 is in a state of idle operation during remaining time of the time segments T1 and T3, thereby causing unnecessary power consumption.